Modelsim is a product of Mentor Graphics and can be easily downloaded with student edition from here: Download Modelsim with Student Licence Technical or accessibility © 2002, 2003 The Board of Regents of the University of Wisconsin System.Modelsim is a simulator and is used to simulate HDL languages including Verilog, VHDL etc. Effective Writing, William Cook's slides based on "Style: Toward Clarity and Grace".How to write a good research paper, Simon Peyton Jones.Optimizations, clock-speek and bonus questions come 2nd. Ask me, the TAs, the peer mentors, or your classmates.įunctionality: Getting a working design is of paramount importance. Plan ahead: You may find that the instructor, TAs, and/or peer mentors will be very inaccessible the night before a deadline.Īsk questions: If you are getting stuck on some problem ask for help. Start early: This project is designed to take a considerable amount of time.
Aligned Single-Cycle Memory Specification. If you need these free late days, I strongly advise you to utilize them for the coding phases (Phases 1-3). I strongly recommend that you do not avail yourself of this option your hard work deserves full credit.Īdditionally, your group will also be allowed three "free" late days for the project. Unless approved by the instructor in advance, you may turn in each phase of the project up to 48 hours late, with a 10% penalty per day, up to two days max.Īny submissions over two days late will receive a zero. Some of these stages are enforced through grading deadlines others are not. The project will progress in several distinct stages. The specifics of the microarchitecture and WISC-SP20 architecture are posted above under "Important Documents." You can self-signup for your group on Canvas using the "Student Groups" tab under "People". Each group must contain at least one person who has not taken ECE 551 already. The project will be completed in groups of two. As with the course homeworks, the CS/ECE 552 Verilog restrictions apply, and all final code is expected to pass the Vcheck program. All components of your design will be written in Verilog. The CS/ECE 552 term project is the complete functional design of a microprocessor called the WISC-SP20. Extra Credit: Due 1159 PM on Tuesday, May 5th. Final Report: Due 1159 PM on Tuesday, May 5th (10% of project grade). Phase 3: Due 1159 PM on Friday, May 1st (30% of project grade). Phase 2.3: Due 1159 PM on Friday, April 17th (10% of project grade). Phase 2: Due 1159 PM on Friday, April 3rd (30% of project grade). Phase 1: Due 1159 PM on Friday, March 13th (15% of project grade). Design Review: Due 1159 PM on Monday, February 24th (4% of project grade). 
Form Project Team: Due 1159PM Friday, February 14th (1% of project grade). 
CS/ECE 552 Intro to Computer Architecture
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